Delay

Given the results of the power optimization (and the simple results of area optimization), the only ``mono''-optimization feasible is the delay optimization.
That it is the maximum delay of critical paths is minimized, disregarding the power consumption and the area occupation, which both increase as the delay diminishes.

Table 5.3: Full-adder: delay optimization 

	Delay [ps]		Energy [pJ]		Area [ $\boldsymbol{\mu}\mathbf{m^2}$]
Full-adder	Pre-opt.	Post-opt.	Pre-opt.	Post-opt.	Pre-opt.	Post-opt.
41inStatic	$\mathbf{0.7}\,\boldsymbol{\mu}\mathbf{m}$ technology
	1781	1080	6.475	40.0	34	195.6
	$\mathbf{0.25}\,\boldsymbol{\mu}\mathbf{m}$ technology
	571.3	415.2	3.155	111.2	17	692.6
41inTSPC (one-stage)	$\mathbf{0.7}\,\boldsymbol{\mu}\mathbf{m}$ technology
	930.6	400.2	2.168	13.390	26	151.7
	$\mathbf{0.25}\,\boldsymbol{\mu}\mathbf{m}$ technology
	276.7	158.3	0.641	3.622	13	80.4

As an example, the delays of the static and dynamic full-adders before the optimization (i.e. all the transistors with minimum width) and after the optimization are presented in table 5.3; in the same table is reported the power consumption of the circuit before and after the optimization of the delay: it is possible to see how the power increases after the delay is minimized.

The criterion that judges when the optimization is over is based on two considerations (see chapter 6, page  for more details on the algorithms implementation, and chapter 4, page  for mathematical foundations):

i)

either if there is a minimum (either the delay figure is strictly convex or, more generally, it has an absolute minimum), then the optimization algorithm find it with an arbitrary accuracy, chosen a priori; or

ii)

if the delay figure is not strictly convex (i.e. is monotone decrescent), then the optimization algorithm goes on minimizing till the rate of decreasing of the delay is below the accuracy.

The former case is more stable from the point of view of the accuracy: given an accuracy, the same optimum solution is found independently from the starting point (i.e. the initial transistor widths) -- the starting point influences only the time it takes to reach the solution, which is unique.
The latter case is somewhat more problematic, since the solution is dependent from the starting point: the decreasing rate of the delay is dependent from the starting point in the multi-dimensional space delay vs. widths. This means that several optimization sessions can give different results, depending on the initial transistor widths in each optimization.

In order to eliminate this ambiguity it is safe to chose a common starting point for all the optimization sessions: the natural choice is to start with all the transistors at the minimum allowed width by the technology. This choice guarantees that changing from an optimization run to another the solution found is always the same, and also it represents a comfortable way for writing the netlist to be optimized, either by a human hand or by a schematic editor.