Optimization examples

In order to show some issues introduced in the previous sections, in the following some CMOS gates will be analyzed. These gates are summarized in the table 5.1, with the second column showing the total number of critical paths in a gate, and the third column showing the total number of MOSFET in a gate. The last two gates are dynamic full-adder, the former composed by complex gate in order to perform the computation in one stage, while the latter is composed only by basic gates (and, or and inverter): this explain why the last full-adder has much more transistor than the first one.

Table 5.1: Basic gates: complexity

Gate	$\char93$ of critical paths	$\char93$ of transistors
Inverter (fig. 5.10)	$2$	$2$
TSPC type n latch (fig. 5.11(a))	$4$	$6$
TSPC type p latch (fig. 5.11(b))	$4$	$6$
TSPC type n and (fig. 5.12(a))	$4$	$7$
TSPC type p and (fig. 5.12(b))	$5$	$7$
TSPC type n or	$5$	$7$
TSPC type p or	$4$	$7$
Static and-or	$12$	$14$
Static and24	3	4
Static or24	3	4
Static parity gate (fig. 5.15)	$24$	$48$
Static full-adder	$34$	$40$
TSPC full-adder (one-stage) (figs. 5.17(a), 5.17(b))	$26$	$13$
TSPC full-adder (basic cells)	$82$	$126$

Figure 5.10: CMOS Inverter

Figure 5.11: TSPC Latches

[Type n] [Type p]

Figure 5.12: TSPC And gates

[Type n] [Type p]

Figure 5.13: TSPC Or gates

[Type n] [Type n]

¹

Figure 5.15: Static parity gate

The table 5.2 shows the delays and the energy consumption of the gates of table 5.1: for each gate it is shown the maximum delay, the average delay, the maximum energy and the average energy of all critical paths. All the simulation are made at the minimum width for that technology (viz. $1\,\mathrm{\mu m}$ for the $0.7\,\mathrm{\mu m}$ technology and $0.5\,\mathrm{\mu m}$ for the $0.25\,\mathrm{\mu m}$ technology).