Power consumption

The calculus of the power consumption of a circuit is quite different from the calculus of the delay: while the delay is a local property of a single critical path (§5.1.1), the power consumption is a global property of the circuit. That is the power consumption of a circuit is not the sum of the power consumption of each critical path²⁰. Even if the definition of ``power consumption'' is global, it is not univocal: the power dissipation of a circuit surely depends on the input conditions. Changing the input states change the overall power dissipation, making some MOSFET conducting, while others not. Again, one must choose a definition of ``power dissipation'' giving a single number, for the purpose of the optimization.
Considering that the objective of the power optimization (hereinafter we will abbreviate power consumption optimization only with power optimization) is the minimization of the total power dissipation, as in the case of delay minimization, a min-max strategy is the most appropriate. Instead of evaluating the power consumption for all the input combinations, we take advantage from the definition of critical path:

Definition 6.4 (Circuit power consumption )   ²¹ The power dissipation of a circuit $P_d$ is:

$$P_d = \max_{n}\left\{ p(\mathsf{C}_n) \right\}$$

where $p(\mathsf{C}_n)$ is the power consumption of the entire circuit when the input conditions of $n$-th critical path are applied.
In this manner it is possible to apply a min-max scheme of optimization, and, at the same time, it is possible to evaluate the power consumption during the same bench of evaluation of the critical path delay, allowing a substantial reduction of the time necessary for the complete evaluation.

In the following, the term power consumption and energy dissipated will be used altogether, since the simple relation between them is:

$$\Bar{E}=\int P(t) dt;$$

this means that the calculation of the mean energy dissipated by a circuit is the integral average of the power and it depends from the simulation time (or the window of time that we are considering), but it does not depends from the frequency of the signals at which the circuit itself operates.

The power consumption of a CMOS circuit is the sum of three term (§3.3, page ):

$$P_{\textrm{TOT}} = P_{\textrm{switch}} + P_{\textrm{short}} + P_{\textrm{sub-th}}$$ (6.29)

the switching power $P_{\textrm{switch}}$, due to the charging and discharging of internal parasitic capacitances; the short-circuit power $P_{\textrm{swhort}}$, due to the simultaneous conduction of n-MOSFET and p-MOSFET, giving thus a direct conducting path from the power supply to the ground for a short time; and the sub-threshold power $P_{\textrm{sub-th}}$, due to sub-threshold conduction of MOS. In a first approximation the first term $P_{\textrm{switch}}$ is proportional to the MOSFET widths in the circuit (greater width means greater capacitance), the second term $P_{\textrm{short}}$ is proportional to switching time and thus it is inversely related to the MOSFET widths (greater capacitance means slower switching time), while the latter term $P_{\textrm{sub-th}}$ is is proportional to the MOSFET widths.

Figure 5.9: HSPICE Energy

As an example, the total power consumption of a single gate is sketched in figure 5.9: as it can be expected the energy is increasing with widths, but it is not convex.

The three terms of equation (5.2) do not weight equally in the sum giving the energy consumption: in order of influence the first term (§3.3.1, page ) is the greater, then comes the second term (§3.3.2, page ) , and finally the third term (§3.3.3, page ) . For a sub-micron technology the second term (the short-circuit dissipation) is about $10\%$ of the first, with the third term (sub-threshold conduction dissipation) about $1\%$ of the first.
It could be expected than with the scaling of the technology (in the deep sub micron field) the first and the second term become comparable, with the third term still a fraction of the other two, giving a power figure not increasing (or even decreasing) with the MOS widths, but also it could be expected that with the scaling down the interconnect capacitances become predominant, making the first term (the power dissipation due to capacitance charging and discharging) still the greatest.

In summary, the power consumption figure of a CMOS circuit is an increasing function of the MOSFET widths, but no assumptions can be made about the convexity of this function.