Circuit delay

Till now the generic word ``delay'' has been used, but now it is mandatory to better define the meaning of delay in a real circuit.

Generally the delay of a CMOS gate, or a CMOS circuit, is defined as the delay between the time when the output is at $50\%$ of its peak value (indicated with $t_o$ in figure 5.2) and the time when the input is at $50\%$ of its peak value (indicated with $t_i$ in the same figure).

Figure 5.2: Delay definition

This definition is good only for theoretical discussion since:

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generally a circuit has more than one input and more than one output;

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not always there is a direct path from the input to the output (let's think about dynamic logic), i.e. not always a change in an input cause directly a change in the output.

So the definition of ``delay'' of a CMOS circuit must be investigated, to produce real number useful for optimization. In order to define it the concept of critical paths has been introduced in [16].
In the following I introduce a new mathematical formulation of the definition of ``critical path''; this formulation will be useful for the automatic solving of the problem of finding all the critical paths in a circuit in §6.2.4 (page ).