Circuit Optimization

=0pt 2=HE2 by = 7=8=18 by 1000 7 by8 =.001by 7 1= 1.051 =-2 -12112=-1000pt goal of the optimization step during a design flow is to obtain from a given design an ``optimized'' design. In the figure 5.1 are showed the various levels of possible optimization.
The optimization level we concern is the inner level, indicated here as dimension optimization. The optimization levels, that is the level at which the designer can apply suitable techniques are, briefly:

Figure 5.1: Design flow

System Optimization

This is higher level of optimization: it concerns the optimization made on user space or kernel space of the applications running in the system subject to the optimization process.

Behavioural optimization

At this level the proper optimization techniques are made by choosing the best algorithm to implement functions.

Logic optimization

This is the optimization made by mapping the given functions or algorithms (from a behavioural optimization) into boolean functions. It is equal to choose the logic gates that implement these functions.

Dimension optimization

This is the lower level of optimization: it is made by choosing the proper transistor dimensions in each gate that implement a logic function. This is the optimization which the efforts of this thesis focus on.

In section 5.1 are shown the three kind of target to be optimized in a real circuit: delay (§5.1.1), power consumption (§5.1.2) and area occupancy (§5.1.3). In particular §5.1.1.1 shows the delay obtained from the Elmore's formula (chapter 2, page ), while §5.1.1.2 shows the delay as it is obtained by HSPICE and FAST (chapter 3, page ).
The section 5.2 contains some application of the mathematical results of chapter 4 (page ): in particular §5.2.2 shows the results of a mono-objective optimization, while §5.2.3 shows the results of a multi-objective optimization. Some conclusions are drawn in section 5.3